Integrated circuits (ICs) are formed on semiconductor wafers using conventional techniques and tools. A typical IC includes thousand of devices (e.g., logic gates, resisters, etc.) each of which may include many complimentary metal oxide semiconductor (CMOS) transistors coupled together via electrically conductive interconnect lines. The devices themselves may also be connected together via electrically conductive interconnect lines.
Many tools are used during the formation of ICs on semiconductor wafers. One tool used repeatedly during IC formation is the chemical mechanical polisher or CMP. Essentially, CMP's are tools that remove excess metal such as tungsten formed on the surface of a wafer. To illustrate, FIGS. 1A-1C show a cross-sectional view of a semiconductor wafer 10 during formation of tungsten plugs to couple electrically conductive interconnect lines on different levels. More particularly, FIG. 1A shows a first dielectric layer 12 deposited on substrate 11, an electrically conductive interconnect line 14, and a second dielectric layer 16. FIG. 1A also shows vias 20 formed within second dielectric layer 16. Vias 20 may have been formed by depositing a photo-resist layer (not shown) over dielectric layer 16, selectively exposing this photoresist layer to light passing through a patterned reticle having via hole patterns, developing and subsequently removing the light exposed photoresist to form a photoresist via mask pattern. Dielectric layer 16 is then etched through this photoresist via mask pattern to create vias 20. Thereafter, the remaining photoresist via mask formed on dielectric layer 16 is removed using conventional techniques. As shown, vias 20 expose underlining electrically conductive interconnect 14.
After formation of vias 20 within the second dielectric layer 16, a layer of tungsten is deposited using conventional techniques. FIG. 1B shows the wafer 10 of FIG. 1A with a tungsten layer 22 deposited thereon. A portion of this tungsten fills vias 20 and will eventually form tungsten plugs that couple electrically conductive interconnect line 14 with another electrically conductive interconnect line (not shown) on a vertically higher level.
After formation of tungsten layer 22, wafer 10 undergoes CMP polishing to remove excess tungsten and form tungsten plugs. FIG. 2 illustrates relevant components of a conventional CMP 24 that can be used for removing excess tungsten from the surface of a wafer, such as wafer 10 of FIG. 1B. The CMP 24 shown in FIG. 2 includes a spindle 26 coupled to a wafer carrier 30. Wafer carrier 30 is configured to receive wafer 10 shown within FIG. 1B. Additionally, CMP 24 includes a platen or polishing pad 32. Wafer 10 is mounted onto carrier 30 such that surface 24 of tungsten layer 22 faces and subsequently engages polishing pad 32.
CMP 24 includes a source (i.e., reservoir, not shown) containing a CMP slurry used in the polishing process for removing excess tungsten from the surface of dielectric layer 16. Typically, a CMP slurry is an acidic or basic aqueous solution that contains metal components such as K3Fe(CN)6, Fe(NO3)3, etc. The acidic or basic solution is chosen based upon the material to be polished in order to induce a chemical reaction. The chemical reaction changes the excess metal to a chemical compound that may be more readily removed by mechanical abrasion of the metal components (e.g., K3Fe(CN)6 or Fe(NO3)3) of the CMP slurry.
The CMP slurry is passed through a conduit (not shown) and onto polishing pad 32. A motor (not shown) rotates carrier 30 via spindle 32. Although not shown, polishing pad 32 is also coupled to a motor for rotating polishing pad 32. Typically, carrier 30 and polishing pad 32 are rotated at different rates but in the same direction as shown.
Carrier 30 rotates wafer 10 relative to polishing pad 32 while wafer 10 engages polishing pad 32 and while the CMP slurry is applied to polishing pad 32 or to the surface 24. This action removes excess tungsten from the surface of wafer 10, while leaving tungsten within vias 20. FIG. 1C shows formation of tungsten plugs 26 after CMP polishing to remove excess tungsten.
The polishing process described above to form tungsten plugs 26 may result in contamination of dielectric layer 16 with metal components (e.g., K3Fe(CN)6 or Fe(NO3)3) from the CMP slurry. These contaminants, if not removed, may affect IC performance characteristics and/or may cause IC device failure to occur at faster rates than usual. In the past, dielectric contaminants were removed using one of two processes. In the first dielectric contaminant removal process, the wafer, such as wafer 10 of FIG. 1C, is rotated at a very high speed while only an organic acid is applied to the surface 28 of the rotating wafer. It should be clear that nothing else (e.g., a polishing pad of a CMP) is applied to surface 28 during this application of the organic acid. In a second dielectric contaminant removal process, an oxide buffing solution is applied to surface 28. This second dielectric contaminant removal process uses a silicon based, oxide slurry buff to physically remove a predetermined amount (e.g., 500 Angstroms) of dielectric 16 that contains the contaminants. While this second dielectric contaminant removal process has been shown to effectively remove metal contamination from the dielectric 16, it does so at the expense of eroding the topography of the wafer, which in turn, reduces process margin and produces higher costs. FIG. 3 illustrates the results of silicon based, oxide slurry buffing a wafer such as wafer 10 shown in FIG. 1C. As can be seen within FIG. 3, the oxide buffing may remove a portion of tungsten plugs 26 and dielectric layer 16 in between tungsten plugs 26.